NIOS connected to IRQ from FPGA but not PIO

[ZhiqiangLiang]

Hi,

I firstly created a new IP, and I add the interrupt sender FPGA_INTS. please see my picture below.

I then connect the FPGA_INTS to irq of NIOS. Please see my picture below.

The generated system.h file is shown in the following picture.

The questions:

1) I notice that a few xxxx_IRQ_INTERRUPT_CONTROLLER_ID  are -1, and a few YYY_IRQ_INTERRUPT_CONTROLLER_ID are 0.  No other value of XXX_IRQ_INTERRUPT_CONTROLLER_ID.  is this correct?

2) the FPGA_INTS is assigned in my verilog code in the IP, and it is 32bit width which is 32 interrupt. how to write C code to accept each interrupt?

3) the FPGA_INTS is a 32bit-register in Verilog. The lowest 4bits of FPGA_INTS is useful, however Platform Designer reports error when I connect the 4bits FPGA_INTS interrupt to irq of NIOS II. so I extend the FPGA_INTS to 32bits in Verilog code and mask [28:4] bit of FPGA_INTS. is what I did correct?

unsigned int HD_irq_context;
void HD_interrupt_handler(void * HD_irq_context)
{
log("in HD interrupt == 0x%x\n", *((unsigned int*)HD_irq_context));
printf("==============================\n");
return;
}
void HD_interrupt_setup( void )
{
void * pISR_contex = ( void *) &HD_irq_context;
alt_ic_isr_register(
BF5V_0_IRQ_INTERRUPT_CONTROLLER_ID,
BF5V_0_IRQ,
HD_interrupt_handler,
pISR_contex,
0x0);
}

[StefanG_Altera]

Hi, as already mentioned on the previous case you created "NIOS handle IRQ from FPGA register":

Your component is exposing 32 bits (as you show in the component editor window), try OR-ing them inside your IP RTL and modify to e.g. expose only one.

The generated system.h file should reflect the IRQ line number and a non "-1" controller-ID, e.g.:
#define BF5V_IRQ 4
#define BF5V_IRQ_INTERRUPT_CONTROLLER_ID 0

Your interrupt registration example code syntax looks correct to me.

Below an example of a custom ip (timer) with a single IRQ out put that I tested on Nios II and works fine, it has only one IRQ. You can use as reference and modify to support more interrupts. The component files are in file ip.zip.

- Instantiation of custom "timer" module:

- system.h:

/*
* timer configuration
*
*/

#define ALT_MODULE_CLASS_timer timer
#define TIMER_BASE 0x81000
#define TIMER_IRQ 2
#define TIMER_IRQ_INTERRUPT_CONTROLLER_ID 0
#define TIMER_NAME "/dev/timer"
#define TIMER_SPAN 16
#define TIMER_TYPE "timer"

- example ot custom-timer interrupt implementation:

..

#include "system.h"
#include "sys/alt_irq.h"
#include "Timer.h"

alt_ic_isr_register (TIMER_IRQ_INTERRUPT_CONTROLLER_ID, TIMER_IRQ, timer_isr, (void*) dummy_ptr, 0);

Timer_init (TIMER_BASE, // Initialize the timer component
50000000, // Write the reload value to the timer, 500ms
Timer_Control_IRQ_EN // 0x04 : IRQ Enable
| Timer_Control_AUTO_ACK); // 0x10 : Auto Acknowledge on Read

[ZhiqiangLiang]

@StefanG_Altera 

Thank you!

I have already done the OR-combine in RTL code of my IP, and output only 1 wire interrupt from my IP.

Currently, the problem is, the generate ID is still -1. please see the following picture.

If I manually change IRQ to 4 and ID to 0, the C code could successfully enter the ISR in my c code. 

The weird thing is that I have to manually change the number after I click "generate BSP".

[StefanG_Altera]

Hi,

I am not sure why the BSP builder is not generating the right macro header values (system.h) for your custom component.

Please try to use my component example as it worked on, my side. You may e.g. have some IRQ port interface settings not set right in your _hw.tcl file. Note: I used Quartus 22.1-std.