Table of Contents
- Introduction
- Environment
- Configuration (HW)
- Configuration (SW)
- Mass Implementation
- Multicore Debugging
- Conclusion
Note: This article is an English translation of this Japanese article by Macnica. Please refer to the original article for updates.
Introduction
The attention to RISC-V has been increasing year by year, and it seems that many manufacturers are developing based on RISC-V. The Nios® V I use this time is also one of the RISC-V based processors, and it is a softcore processor developed by Intel. This article is an experimental article about implementing Nios® V to the limit on Agilex™ 7, thinking about doing something interesting with RISC-V.
Environment
This time, since we are using Intel FPGA and Nios® V, we will use the following:
- Intel® Quartus® Prime Pro Edition Software Version 22.2 for Windows
- Ashling* RiscFree* IDE for Intel® FPGAs
We will use the following for Agilex™ 7:
Configuration (HW)
This time, to implement many Nios® V, we have created a submodule with Nios® V, and are instancing that module in the top level. The configuration of the submodule includes:
- Nios® V/m processor
- On Chip RAM
- JTAG-UART
These three are the minimum requirements for operation confirmation. The top level includes:
- CLK
- Reset
- Submodule (Nios® V)
- ISSP Reset
You may not be familiar with ISSP, but understand that we are using HW logic with ISSP to toggle the Reset because the development kit used this time does not have a reset button for FPGA. The block diagram of this configuration is as follows. (Orange is Bridge, and purple is IP, color-coded.)
In this configuration, the On chip RAM for Nios® V execution memory is generated with 128kByte. For details, please refer to the capture of the Platform Designer in "Mass Implementation".
This time, since we will not perform a standalone operation confirmation, we have constructed it to only run the elf file in RAM with a debugger without considering detailed settings such as Reset Vector or Boot methods for each Nios® V.
Configuration (SW)
The software is a simple program that outputs to the JTAG console. Since we implement multiple Nios® V, it is better to write the program so that the outputs from different cores can be distinguished. Please refer to the final outputs at the end of section Multicore Debugging.
Mass Implementation
This configuration is created in Platform Designer. Since we only need to instance the submodules in the top level, we are lucky that the top level remains clean, although it took time to generate. First, let's check with only one Nios® V.
As explained earlier, it appears that only one Nios® V submodule is implemented in the Platform Designer system. Below is the top level system diagram (the red frame is the Sub module).
This is the Sub Module (the red frame is Nios® V/m processor).
The compilation result is below.
Even though we used 128kB Onchip RAM, it is still only 1% utilized. Next, let's try with 10 units. To make it easier later, we have created a submodule that implements 10 submodules and instance it in the top level. Below is the compilation result.
Roughly, the RAM block usage is 1% per Sub module. Let's go bold and implement 100 units.
We barely managed to implement it! It's okay to implement 100 units!!
Although we think we can implement a few more, as the RAM resources are over 90%, we will settle with 100 units for now.
Multicore Debugging
Finally, I would like to write about debugging when implementing multiple units. For the Nios® V development environment, we use Ashling* RiscFree* IDE for Intel® FPGAs introduced in Chapter 2. It can be downloaded together with Intel® Quartus® installer, so please install it together. Here, I will omit the steps for launching Ashling* RiscFree* IDE for Intel® FPGAs and importing the project.
The build process was referenced from the article below:
Development Procedure for Nios® V Projects using Ashling* RiscFree* IDE for Intel® FPGAs
After you have built the projects, first create a Debug configuration for each CPU. You can select which CPU to create for from the Core selection in the Debugger tab, as shown below.
After setting and creating the Debug configuration for each CPU, group them with Launch Group to execute them simultaneously.
This completes the Debug configuration. Next, prepare the console output destination. This time, due to screen display limitations, we will display the output in each Nios® V command shell. Launch the Nios® V command shell for each CPU and execute the following command:
#juart-terminal -c <change for each CPU> -d <device number> -i <instance number> juart-terminal -c 1 -d 0 -i 0
With this command, each Command shell will be linked to the JTAG console. (The last number in Core selection corresponds to the argument of -i.)
Select the Group created earlier and press Debug. By default, it will break at the start of the main function, so you can add breakpoints, check register and variable values for each source to debug. The execution result this time is shown below. We captured the situation where the JTAG console is running simultaneously.
Conclusion
This time, I implemented many Nios® V just for fun, but it took a lot of time for tasks such as compilation time and Platform Designer hierarchy design. It was quite difficult for an article started with a light heart. However, since I think there are few people who actually perform this configuration, I hope you will find the multicore debugging part helpful.
Notices & Disclaimers
Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. The products described may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade. Nios is a trademark of Intel Corporation or its subsidiaries.
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