Over 4GB PCIe BAR Size Issue

[danield17]

Hi,

I created a design that utilizes the Arria 10 Hard IP and an EMIF.

On my board, I have 8GB of DDR memory, and I wanted to connect one of the PCIe BARs to the EMIF so I could read from and write to the DDR.

I encountered an issue where the OS (I tried both Windows and Linux) detects the BAR size but cannot use it. I was unable to read from or write to this BAR.

When I used the Address Span Extender to reduce the BAR size to 2GB, I was able to read and write. However, when I increased it to 4GB or above, it no longer worked.

I also tried enabling "Above 4G Decoding" and "Resizable BAR" in the BIOS, but it made no difference.

Has anyone else encountered this issue?

[AdzimZM_Intel]

Hi Daniel,

I'm Adzim from Altera. I will assist you in this case.

Have you verified that you are able to access 8GB DDR before? -maybe use difference design such as EMIF example design.

We need to make sure the EMIF IP setting is set correctly for the DDR that you used.

Can you provide the EMIF IP setting (can share the snapshot of the EMIF IP setting) and the DDR/memory datasheet?

Regards,

Adzim

[danield17]

Hi Adzim,

I’ve already created a design that uses DMA and the Address Span Extender, with my BAR set to 2GB, and everything worked fine.

I haven’t tried the EMIF example design, but I’ve confirmed that I can read and write to the DDR using both the DMA and the BAR master.

After investigating the issue, I found that read and write operations only work for me when the PCIe Hard IP is configured with burst enabled for the BAR2 master.

Is there a reason it only works with the burst master? Could it be something internal to the PCIe IP?

Did I miss something that would cause it to work only in burst mode?

Do you still want snapshots and the DDR datasheet? If so, how should I provide the snapshots—images?

Regards,

Daniel

[ventt]

See below message.

[AdzimZM_Intel]

Hi Daniel,

"Do you still want snapshots and the DDR datasheet? If so, how should I provide the snapshots—images?"

• Yes, you can send the EMIF IP setting in the PDF and DDR datasheet in PDF.
• I know the operation is running okay, but let start to debug at EMIF IP first.
• Then, can check the other.

For the burst mode questions, the PCIE expert will comment later.

Regards,

Adzim

[ventt]

Hi Daniel,

I will look into your issue with the PCIe IP.

Could you please share the pcie.ip file used in your design? I would like to understand further the parameters and settings you have configured.

Thanks.
Best Regards,
Ven

[danield17]

Hi Ven,

Sorry for the delay in getting back to you.

I’ve attached the PCIe IP file along with the Quartus project in case you’d like to take a look.
As I mentioned earlier, everything worked fine when I was using the burst master.
The issue only came up when I used the BAR2 master without bursting.
The DMA master interface is also connected to the EMIF, and with DMA, both reads and writes work as expected. But with the BAR2 master, it didn’t work.

Best Regards,

Daniel